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Freescale Semiconductor /MK61F15WS /DDR /CR51

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Interpret as CR51

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DLLRSTDLY0DLLRADLY0PHYWRLAT 0RESERVED

Description

DDR Control Register 51

Fields

DLLRSTDLY

DLL Reset Delay
DLLRADLY

DLL Reset Adjust Delay
PHYWRLAT

PHY Write Latency
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data